October 2018

NU Power Electronics Research Lab



NU Power Electronics Research Lab comprises 3 professors:

– Dr. Alexander Ruderman, Associate Professor, SEng, Co-Director;

– Dr. Yakov L. Familiant, Assistant Professor, SST, Co-Director;

– Dr. Tohid Alizadeh, Assistant Professor, SST,


researchers from National Lab Astana:

– Dr. Viktor Ten; Head of Intellectual Systems and Energy Efficiency Laboratory;

– BSc Anar Ibrayeva, Research Assistant in Intellectual Systems and Energy Efficiency Laboratory,


SEng Lab Technician MSc Ansar Berdygozhin and undergraduate students:


– Kenessary Koishybay (SST);
– Rassul Bairamkulov (SEng);
– Janysbek Kusmangaliyev (Seng);
– Ramazan Abdikarimuly (SEng);
– Ainur Zhaikhan (SEng);
– Aidana Daulbayeva (SEng);
– Altynay Smagulova (SEng);
– Anvar Khamitov (SEng);
– Shakhnazar Salden (SEng);
– Nurislam Tursynbek (SEng);
– Yerbol Akhmetov (SEng);
– Aidar Zhetessov (Seng).

Though some of the research topics below were addressed by many other researchers, there is no in-depth understanding and simple practical solutions ready for use in an everyday engineering practice.


  1. Multilevel PWM Voltage and Current Quality (THD) Evaluation

Accurate analytical calculation and simple (approximate) smooth formulas (functionally equivalent to Matlab/Simulink or PSIM FFT THD tool but gives an in-depth understanding of a level count and modulation index influence).

  • PWM Voltage Quality (THD) for Single- and Three-Phase Multilevel Inverters
  • PWM Current Quality (THD) for Single-Phase Multilevel Inverters (three-phase case is much more complicated due to zero sequence impact)
  • PWM Voltage and Current Quality (THD) for Single-Phase Multilevel Inverters in the presence of LC- and LCL-filters

The work is done in collaboration with University of Bologna, Bologna, Italy.


  1. Optimal Voltage and Current Quality (THD) for Staircase (Step) Modulation

Accurate analytical-numerical calculation and simple (approximate) smooth formulas.

This is about finding optimal switching angles (different for voltage and current) accounting for all switching harmonics by means of numerical constrained optimization. Most of the published research ignore high order harmonics (THD underestimation) and use global optimization formulation (bringing THD and fundamental magnitude constraint together into a single target function with empiric weight coefficients) and metaheuristic optimization / soft computing – genetic, particle swarm, neural networks, bee, bat etc etc algorithms that have to run long hours and deliver sensitive unstable solutions – no unique smooth switching angles dependence on fundamental magnitude (modulation index).

2.1. Multilevel Optimal Voltage and Current Quality for Uniformly Distributed Voltage Levels for Single- and Three-Phase Converters

2.2. Multilevel Optimal Voltage and Current Quality for Non-Uniform Voltage Level Distribution (unequal cascade H-bridge converter DC voltage sources) for Single-Phase Converters (three-phase case is much more complicated)

For grid-connected and similar applications, current quality may essentially change with a relatively small variation of fundamental voltage magnitude.


  1. Combining SHE and Minimal THD Approaches

So far there are two different basic approaches – Selective Harmonic Elimination (SHE) and THD optimization (minimization). Our idea is to bring them together. If there is enough switching angles (relatively high level count for staircase modulation or multiple switching between adjacent voltage levels) then some degrees of freedom may be used to eliminate selected low order harmonics while other – to minimize the THD.


  1. Capacitor Voltage Natural Balancing in Different Multilevel Voltage Source Converters

In principle, there are two ways to balance capacitor voltages in multilevel converters. The first one is natural balancing. Natural balancing means that capacitor average voltages automatically (naturally) settle at their required voltage levels due to appropriate converter voltage modulation strategy without a measurement and special balancing control effort.

The major problem with natural balancing is possible poor (slow) balancing rate meaning that theoretical voltage balancing time constant becomes too large and even tends to infinity. A practical operation of such a converter with low balancing stability margin is impossible because, due to non-idealities like asymmetry in switching times and other second-order effects unaccounted on modelling stage, capacitor voltages may become unstable and run-away from their balanced values.

Literature review shows that, having faced poor natural balancing problem, most of the researchers moved to active balancing without getting an in-depth understanding of poor natural balancing root causes. Active balancing assumes multiple capacitor voltage measurement (additional hardware) and control-based stabilization (additional control effort – CPU computational load). The advantage of an active balancing is fast capacitor voltage balancing rate. However, this may come at the expense of compromising optimal voltage quality of nearest switching and uneven switching and conductivity losses distribution across different semiconductor devices.

In fact, some active balancing people have the courage to acknowledge that active balancing methods are not good in a steady-state operation conditions. This again emphasizes the importance of development of natural balancing voltage modulation strategies that deliver good enough (or best) natural balancing behaviour. Another important practical aspect is fault tolerance of converters with active balancing. In case of capacitor voltage sensor failure such a converter may keep functioning by applying good natural balancing PWM.

The purpose of the research is to study natural balancing mechanisms and demonstrate improved natural balancing PWM strategies for some multilevel converters that good natural balancing PWM strategies for them were not reported so far (like hybrid topologies with capacitor H-bridges).

Another possibility to improve natural balancing rate is to use a balancing booster (additional piece of hardware – tuned resonant circuit). Balance booster may assist in achieving good natural balancing in the classic 3-level NPC converter.  There is no good practical balance booster theory developed so far.

The work is done in collaboration with Silesian University of Technology, Gliwice, Poland.


  1. Reconfigurable Switched Capacitor Converters (SCC) with Multiphase Balanced Switching and Multiple Outputs

SCC doesn’t use inductive components and may be advantageous for certain applications like on-die and on-chip DC-DC power supplies. Multiphase switching provides different output voltage (Target Ratio – TR) capability thus expanding functionality. Some of our recent research directions in the field include:

5.1. A concept of balanced switching – multiple (redundant) use of switching states to make charge flow to a load as smooth as possible.

5.2. Novel TRs for the known topologies – FCC and Fibonacci SCC.

5.3. Minimal Norm Principle. Sometimes an amount of available topologies for a certain TR is larger than its switched and filter capacitors count. In this case, charge flow equations become underdetermined and the known solution is to give up with some redundant topologies. Then charge flow becomes essentially non-uniform that causes losses (equivalent resistance) and output voltage ripple increase (sometimes there is even reverse charge flow from the load). The Minimal Norm Principle suggests that the nature selects the unique solution of the underdetermined charge flow equations that has the minimal Euclidean norm. Mathematically this is given by a pseudo-inverses matrix. The principle is confirmed by simulations for single-ended SCC and the use of redundant topologies is most beneficial from balanced switching and minimal equivalent resistance perspectives.

5.4. SCC with Dual (Multiple) Reconfigurable Outputs. Using shared capacitors allows for reducing parts (capacitors, switches) count. As the dual output SCC charge flow equations are typically underdetermined, they are solved using Minimal Norm Principle. We are particularly focused on dual output SCC with practically decoupled outputs (no cross-coupling). If the coupling exists, there is no reciprocal equivalent circuit that may seem somewhat surprising and unexpected.


  1. PWM Induced Losses in Iron Cores of Electrical Machines

PWM controlled voltage of electrical machines produces additional losses. While PWM copper loss (Harmonic Loss Factor) due to PWM current ripple is straightforward, PWM iron loss is less evident. For relatively high PWM frequency PWM eddy current iron loss becomes a dominant PWM iron loss mechanism and does not much depend on switching frequency. Local eddy current time distribution is similar to that of the PWM voltage ripple. Therefore, the problem of finding integral PWM eddy current iron loss is quite similar to that of integral PWM voltage quality and requires double time integration (averaging squared eddy current / voltage ripple on a PWM period and on an AC fundamental one). For non-salient pole rotor machines, under some simplifying assumptions integral PWM iron loss dependence on modulation index is given by a formula confirmed by experiments.  The important practical consequence is that only one PWM iron loss FEM simulation / characterization is required. Quantified PWM iron loss is then easily scaled for any operation.

The known PWM iron loss separation / characterization methods assume sinusoidal and PWM excitation no-load experiment for rotating motor. The accuracy of such experiment is low due to subtraction of close quantities. It is suggested to make a PWM iron loss characterization experiment at stall (locked rotor) with special bipolar modulation. It is simple (no rotation) and accurate (no fundamental loss to separate – all the loss into machine is PWM one).

The work is done in collaboration with Tampere University of Technology, Tampere, Finland.